Field Effect Transistors (FETs) are transistors which rely on an electric field to control the shape, and hence the conductivity, of a channel of one type of charge carrier in a semiconductor material. FETs typically use a p-n junction for a gate. There are several different types of FETs, including Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs) and Metal Semiconductor Field Effect Transistors (MESFETs).
MESFETs can be formed using Silicon on Insulator (SOI) technology. SOI technology uses layered silicon-insulator-silicon substrates in the manufacture of semiconductor devices. MESFETs typically use a Schottky junction for a gate as opposed to using a p-n junction as MOSFETs typically do. MESFETs can be made in which dopants are implanted into the device to achieve doping concentrations that enable complementary n- and p-channel Schotkky Junction Transistor (SJT) behavior. A Schottky junction (or barrier) is a potential barrier formed at a metal-semiconductor junction that has rectifying characteristics. A Schottky barrier typically has a lower junction voltage and a narrower depletion region than a p-n junction.
Each new complimentary metal-oxide-semiconductor (CMOS) process technology scales the MOSFET to smaller dimensions resulting in higher doping levels and lower operational voltages. However, a number of analog circuit applications still require the ability to support higher voltages. MESFETs capable of higher voltage operation than MOSFETs can be constructed on commercially available SOI CMOS without process modifications.
One approach to forming a MESFET using available SOI CMOS process technology is described in U.S. Pat. No. 6,864,131, filed on Mar. 17, 2003, entitled “Complementary Schottky Junction Transistors and Methods of Forming the Same” (the '131 Patent). Of particular note, with this approach, the silicide block step is used to separate the silicide that forms the Schottky gate from the silicide that forms the low-resistance contacts to the source and drain of the MESFET structure. However, such a silicide block step is generally used to form relatively large resistive components in either silicon or polysilicon and is typically a relatively low resolution step as compared to the rest of the SOI CMOS process flow. Since the respective spaces between the Schottky gate and the source and drains are key features in such a MESFET structure, the minimum size of the MESFET structure that is achievable using such an approach is typically constrained by the resolution of the silicide block step.